For our requirements we need at least project trainee engineers with Bachelor’s Degree in Computer Science or Electronics.As the ongoing projects are research based hence Masters shall be desirable but not mandatory.
Below is the list of projects that are either completed and need enhancements or need to be started from the scratch.
Assignment will be for minimum period of 3 months.
CPU architecture(desirable),VHDL/Verilog(mandatory),Algorithm implementation in HDL,FPGA architeture, C/Python based programming(mandatory).
ASIC, SOC front end and backend/Physical design, Database integration, Applicaton development, exposure to Vitis/Xilinx, SoC builder -Altera and Cypress.
AI, ML, DL for Healthcare, Automotive industry.
(Please send your CVs to firstname.lastname@example.org)