Me and Bharat with Satish reached N**** on time. There were 3 engineers -2 Europians and 1 Indian. After a brief introduction about ourselves I went with the Indian N*** interviewer,who was a Project Manager.In the meanwhile Bharat was having interview with Europian interviewers. My experiences and questions :

Interview-1 The Indian interviewer told me that he is the Project Manager for the big IP(not SoC),that is actually a Physical(PHY Layer) IP,which has some digital logic being implemented and a seperate RF(Radio Frequency) module .These two divisions make it a complete Analog Mixed Signal IP(AMS).

He asked me about the last project that involved ARM based AHB and also AXI bus interfaces.I could answer all the questions and later he said that they are also using the similar environment (w.r.t. ARM processors,controllers etc). Then he asked me about the BFMs (Bus Functional Models) we were using,if at all.I told him that for AHB we designed our own BFMs in Verilog and for the AXI we used VMT-Vera Modelling Technology based Synopsys Designware VIPs.

Then asked me about my role in the project,and I told that I was involved with the testbench enhancements from Verilog to IEEE 1800 System Verilog for the Random based coverage driven verification from Directed Verification,and told about all the basic building blocks with corresponding language based constructs in System Verilog.

Also told that I was also involved with writing C based SoC level patterns ,Verilog based BFM pattrerns,Fomal Verification,Assertion Based Verification,temporal coverage and covergroup coverage that produces the Functional Coverage. He asked me about the C based environment and how and what the testcases written in C doing.I could answer them all w.r.t. ARM platform internal functionality(FIQ,IRQ,different modes of Operation of ARM and interaction with other submodules).

He asked me about VHDL,that what is the differene in VHDL and System Verilog and I told him w.r.t. fork-join,OOD and my perception of confidence level to decide what language must be used .I said that SV is more effcient when it comes for verification w.r.t. Assertions,Coverage,Randomisation etc. He agreed with me and said initially we’ll be uising VHDL and later can go for some better approach if proposed and accepted. It took almost 30 minutes to finish the interview!!! Interview-2 Two europian interviewers told me something that Indian never told me.They categorically said that they require verification engineer who has worked on the Signal Processing related algorithmic verifiactions.

Then they asked about difference between Procedure and Function ,configurations in the VHDL. There were questions in each and every project I have handled (sort of I tell they listen).Then they inquired whether I have finished work in hand and am free right now and how soon can I join. They asked at what stage I have worked with VHDL,and I told that it was in fpga designing(RTL ) phase.Some questions w.r.t. signal,variable were also thrown. At last they asked me what will be the verification strategy for the “Signal Processing Algorithm Based IP”-w.r.rt. tools,methodology etc.And then we had some discussion about Formal Verification tool(Magellan,IFV) which I had used sometme back!!! It took almost 35 minutes to finish the interview!!!

Comments are closed.